1. Field of the Invention
The present invention relates to an automatic trace determination method and apparatus for determining optimal trace positions from pads to corresponding vias on a substrate.
2. Description of the Related Art
In a semiconductor package such as PBGA and EBGA, electrode terminals of a semiconductor chip are electrically connected with pads (for example, bonding pads or flip-chip pads) and the pads are connected with vias (a land), and the vias are also connected with each other by traces (i.e., signal traces). Traces in the semiconductor package at least have to satisfy design rules in that clearances between traces and so on can be secured and there is no unnecessary trace crossing. For example, a designer typically designs a wiring route of a semiconductor package by trial and error on a virtual plane using a CAD system.
For example, Japanese Unexamined Patent Publication No. 2002-08300 discloses an exemplary wiring pattern design method in which only a wiring route is determined in advance in a rough wiring process and, then, in a trace formation process, traces are provided uniformly by checking clearances (lines and spaces) according to actual design rules.
Further, for example, Japanese Unexamined Patent Publication No. 10-214898 discloses a wiring method that adopts an any-angle wiring so that a wiring area can be utilized efficiently and, at the same time, clearances between the wirings and widths of the wirings can be increased in a free region.
If wirings in a semiconductor package at least satisfy design rules, it can be said that a certain measure of success is achieved. In effect, however, it is often required not only that the wiring pattern satisfies the design rules but also that the wiring pattern is a “visually beautiful pattern” that is arranged with order and regularity.
FIG. 20 is a diagram illustrating an example of traces arranged on a substrate without order and regularity, and FIG. 21 is a diagram illustrating an example of traces arranged on a substrate with order and regularity. Hereinafter, when traces are shown in the accompanying figures, the shown traces are at least a portion of the traces on the substrate. Further, FIG. 22 describes legends of symbols for vias, pads and traces indicated in the figures attached to this specification. Hereinafter, the legends of FIG. 22 apply to the figures showing the vias, pads and/or traces.
In comparison with the traces shown in FIG. 20, the traces shown in FIG. 21 are bent at bending points that are arranged in a line with some regularity and the number of the bending points is less than that in the case of FIG. 20. Further, the traces shown in FIG. 21 are well balanced with left-to-right symmetry. On the other hand, the wirings shown in FIG. 20 do not have remarkable symmetry and have even nonuniformity of integration density.
In comparison with the wiring pattern without regularity as shown in FIG. 20, the wiring pattern arranged with order and regularity as shown in FIG. 21 has shorter wiring length and, therefore, it can be more economical and it can be manufactured more easily and it has a lower rate of occurrence of failure in the manufacturing process. Further, it is electrically stable. Still further, in the substrate in which the wiring pattern is well balanced, which is deformed substantially uniformly even when it is deformed, for example, due to heat, defects such as a short circuit or breaking of traces is not likely to occur. Moreover, the semiconductor packages having the wiring pattern with order and regularity to some extent are visually more beautiful and, as a result, often advantageous when selling the semiconductor packages.
Typically, a designer designs a wiring route of a semiconductor package by trial and error on a virtual plane while actually manipulating a CAD system depending on own experience and intuition. FIGS. 23-26 are diagrams for describing a specific example of a related-art manual pattern design by trial and error. In this specification, hereinafter, V is a reference symbol of vias, a character B combined with a numeral such as 1 or 2 is a reference symbol of pads, and a character W combined with a numeral such as 1 or 2 is a reference symbol of signal traces (wires). Further, a virtual check line used for checking clearances (lines and spaces) between traces or between traces and vias is referred to as a clearance check circle that is designated by alternate long and short dashed lines in the figures.
Typically, in fan-in/out wirings, considering a subsequent solder resist process, traces W1-W6 are drawn out at a minimum in the same direction as the pads B1-B6. The length of the trace drawn out at a minimum in the same direction as the corresponding pad is referred to as the “minimum length”, in this specification. For convenience, a portion of the trace drawn out from the corresponding pad having the “minimum length” is particularly referred to as the “minimum trace”. In fan-in/out wirings, because a solder resist is applied around the pads, a bending point cannot be provided in a region along the minimum length from the pad and the trace can be bent only at a position remote from the pad by the minimum length or more.
Typically, as semiconductor packages are miniaturized and integrated more and more, the clearances between pads and vias tend to become narrower.
For example, as illustrated in FIG. 23, when bending points are provided while securing clearances between the minimum traces, each minimum trace may be extended appropriately so that the bending points can be aligned substantially in a line (as shown by a dotted line in the figure). However, in the example of FIG. 23, the clearance between the trace W6 and the via V cannot be secured sufficiently and, as a result, a clearance error will occur.
Further, for example, as shown in FIG. 24, when bending points are provided on traces that are separated from each other by a minimum clearance to secure the distance between the trace W4 and the via V, the bending points are not aligned in a line regularly because the pads are not arranged equidistantly.
Also, when the pads have an elliptical shape and the pads are not oriented in an identical direction, a clearance error may occur. For example, as shown in FIG. 25, when the pad B3 is oriented in the direction to approach the pads B2, if the wiring pattern is designed unnaturally so that the bending points are aligned in a line (as shown by a dotted line in the figure), the clearance between the traces W2 and W3 cannot be secured sufficiently and a clearance error will occur. On the other hand, for example, as shown in FIG. 26, when the pad B3 is oriented in the direction to be separated from the pad B2, if the wiring pattern is designed unnaturally so that the bending points are aligned in a line (as shown by a dotted line in the figure), the clearance between the traces W3 and W4 cannot be secured sufficiently and a clearance error will occur.
At present, in order to manually design a so-called “beautiful pattern”, a designer has to design by trial and error according to his own judgment so that the bending points can be aligned in a line and the pattern can be well balanced as much as possible, while securing the necessary clearances.
In such manual pattern design by trial and error in the related-art, even if a wiring pattern with order and regularity is achieved, design quality and time required for design greatly depend on the designer's skill, experience, intuition and the like. Also, in manual pattern design by trial and error, as the required pattern becomes more complicated, the effort, time and difficulty for achieving the wiring pattern with order and regularity is increased. Further, unevenness in quality of finished products is also increased. In reality, because the manual pattern design by trial and error requires a half or full day's work and it is not economical to waste further time for pattern designing, the designer has to compromise with a certain design quality.
In view of the above problems, it is an object of the present invention to provide an automatic trace determination method and apparatus for automatically determining optimal trace positions using computation so that traces from pads to corresponding vias on a substrate can have order and regularity.